-- Testbench

library IEEE;
use IEEE.Std_Logic_1164.all;

entity testbench1 is
   generic (clkPeriod : time := 100 ns;
            resetTime : time := 20 ns);
end entity testbench1;

-- Test prawidlowego dzialania ukladu
architecture test1 of testbench1 is
  signal testCLK    : std_logic := '0';
  signal testRST    : std_logic;
begin
  -- zegar
  process(testCLK) is
  begin
    testCLK <= not testCLK after clkPeriod / 2;
  end process;
  
  -- uklad resetujacy
  process is
  begin
    -- uklad zostaje raz zresetowany, a nastepnie
    -- rozpoczyna normalna prace
    wait for 40 ns;
      testRST <= '0';
    wait for resetTime;
      testRST <= '1';
    wait for 500 ms;
  end process;
  
  -- procesor testowany
  PROCESSOR: entity work.processor1
    port map (
        CLK   => testCLK,
        RST   => testRST
    );
end architecture test1;

-- Test resetu
architecture test2 of testbench1 is
  signal testCLK    : std_logic := '0';
  signal testRST    : std_logic;
begin
  -- zegar
  process(testCLK) is
  begin
    testCLK <= not testCLK after clkPeriod / 2;
  end process;
  
process is
  begin
    -- uklad zostaje resetowany
    -- co pewien zmienny odstep czasu
    wait for 40 ns;
      testRST <= '0';
    wait for resetTime;
      testRST <= '1';
    for i in 2 to 7 loop
      wait for i * 300 ns;
        testRST <= '0';
      wait for resetTime;
        testRST <= '1';
    end loop;
  end process;
  
  -- procesor testowany
  PROCESSOR: entity work.processor1
    port map (
        CLK   => testCLK,
        RST   => testRST
    );
end architecture test2;